SUBJECT NAME: VLSI DESIGN. SUBJECT CODE: EC UNIT I CMOS TECHNOLOGY. PART –A (2 MARKS). 1. What are four generations of Integration. EC / EC64 VLSI Design 2 Marks With Answers ECE 6th Semester Regulation | BE Electronics and Communication Engineering. Sixth Semester. 2 MARK QUESTION AND ANSWERS. ECVLSI DESIGN is CMOS technology? Complementary Metal Oxide Semiconductor (CMOS)in which.

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What are the applications of chip level test techniques?

What is pull up device? It can be drawn much easier and faster than a complex layout.

Channeled gate array Channel less gate array Only the interconnect is customized Only the top few mask layers are customized The interconnect uses predefined No predefined areas are set aside for spaces between rows of base cells routing between cells. But at the same time, latch based design is more complicated and has more issues in min timing races. Other adder structures use logic optimizations to increase the performance carry bypass, carry select, carry look ahead. What are the self-test techniques?

What is Stick Diagram? Only the top answerss mask layer customized customized. What is a FPGA? These include serial-shift clocks and update clocks. By using two operating modes, active and standby for each function blocks. Green — n-diffusion Red- polysilicon Blue —metal Yellow- implant Black-contact areas. What is the difference between latches and flip flops based mars With short channel devices the ratio between the lateral and vertical dimensions are reduced. If the channel is initially doped lightly with p type impurity a conducting channel exists at zero gate voltage and the device is said to operate in depletion mode.


What are the characteristics of FPGA? Give the different symbols for transmission gate. The current between drain and source terminals is constant and independent of the applied voltage over the terminals.


Methods of timing control: Latch based design and flop based design is that latch allows time borrowing which a tradition flip flop does not: A ripple carry adder has a performance that is linearly proportional to the number of bits.

The effective length of mrks conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel. What are the different MOS layers? These are especially important tools for layout built from amswers cells.

Different types of oxidation? The difference between the earliest reaching flip flop and latest reaching flip flop for a same clock domain. Transistors with channel length less than 3 5 microns are termed as short channel devices. Give the different symbols for transmission gate.

No else statement Syntax: What is mean by power and power dissipation? The number of transistor is getting doubled in every 18 months based on moore’s law Higher speed of operation: Event-based timing control 3.


Each bit combination of the input variables is called an address. These tests assert that all the gates in the chip, acting in concert, achieve a desired function. A device connected so as to pull the output voltage to the upper supply voltage usually VDD is called pull up device. It is used to convey information through the use of color code. Mention the ideas to increase the speed of fault simulation? What is metastability and list the steps to prevent it? In a PAL, the device is programmed by changing the characteristics if the switching element.

Regular delay control 2. This provides sufficient power saving.

This is called boundary scan. Write notes on functionality tests? Define elmore delay model.

EC VLSI DESIGN Important Part A 2 Mark Part B 16 Mark Question Bank

A simulation is run with no faults inserted, and the results of this simulation are saved. A carry glsi adder consists of a simple ripple carry adder with a special speed up carry chain called a skip chain.

This makes MOS dynamic circuits faster.